- Código RS:
- 188-2835
- Nº ref. fabric.:
- W972GG6KB25I
- Fabricante:
- Winbond
- Código RS:
- 188-2835
- Nº ref. fabric.:
- W972GG6KB25I
- Fabricante:
- Winbond
Documentación Técnica
Legislación y Conformidad
Datos del Producto
The W972GG6KB is a 2G bits DDR2 SDRAM, and speed involving -18, -25/25I, and -3/-3I.
Double Data Rate architecture: two data transfers per clock cycle
CAS Latency: 3, 4, 5, 6 and 7
Burst Length: 4 and 8
Bi-directional, differential data strobes (DQS and /DQS ) are transmitted / received with data
Edge-aligned with Read data and center-aligned with Write data
DLL aligns DQ and DQS transitions with clock
Differential clock inputs (CLK and /CLK)
Data masks (DM) for write data
Commands entered on each positive CLK edge, data and data mask are referenced to both edges of /DQS
Posted /CAS programmable additive latency supported to make command and data bus efficiency
Read Latency = Additive Latency plus CAS Latency (RL = AL + CL)
Off-Chip-Driver impedance adjustment (OCD) and On-Die-Termination (ODT) for better signal quality
Auto-precharge operation for read and write bursts
Auto Refresh and Self Refresh modes
Precharged Power Down and Active Power Down
Write Data Mask
Write Latency = Read Latency - 1 (WL = RL - 1)
Interface: SSTL_18
CAS Latency: 3, 4, 5, 6 and 7
Burst Length: 4 and 8
Bi-directional, differential data strobes (DQS and /DQS ) are transmitted / received with data
Edge-aligned with Read data and center-aligned with Write data
DLL aligns DQ and DQS transitions with clock
Differential clock inputs (CLK and /CLK)
Data masks (DM) for write data
Commands entered on each positive CLK edge, data and data mask are referenced to both edges of /DQS
Posted /CAS programmable additive latency supported to make command and data bus efficiency
Read Latency = Additive Latency plus CAS Latency (RL = AL + CL)
Off-Chip-Driver impedance adjustment (OCD) and On-Die-Termination (ODT) for better signal quality
Auto-precharge operation for read and write bursts
Auto Refresh and Self Refresh modes
Precharged Power Down and Active Power Down
Write Data Mask
Write Latency = Read Latency - 1 (WL = RL - 1)
Interface: SSTL_18
Especificaciones
Atributo | Valor |
---|---|
Tamaño de la Memoria | 2Gbit |
Organización | 256M x 8 bit |
Clase SDRAM | DDR2 |
Transmisión de Datos | 800MHZ |
Ancho del Bus de Datos | 16bit |
Ancho del Bus de Direcciones | 17bit |
Número de Bits de Palabra | 8bit |
Tiempo de Acceso Aleatorio Máximo | 0.4ns |
Número de Palabras | 256M |
Tipo de Montaje | Montaje superficial |
Tipo de Encapsulado | WBGA |
Conteo de Pines | 84 |
Dimensiones | 12.6 x 8.1 x 0.6mm |
Altura | 0.6mm |
Longitud | 12.6mm |
Tensión de Alimentación de Funcionamiento Mínima | 1.7 V |
Ancho | 8.1mm |
Temperatura de Funcionamiento Mínima | -40 °C |
Tensión de Alimentación Máxima de Funcionamiento | 1.9 V |
Temperatura Máxima de Funcionamiento | +95 °C |
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