AEC-Q100 Registro de desplazamiento controlado por tensión, M74VHC1GT126DF2G, SC 5 pines

High Speed: tPD = 3.5ns (Typ) at V CC = 5V
Low Power Dissipation: ICC = 1μA (Max) at TA = 25°C
TTL-Compatible Inputs: VIL = 0.8V, VIH = 2.0V
CMOS-Compatible Outputs: VOH > 0.8VCC , VOL < 0.1VCC @Load
Power Down Protection Provided on Inputs and Outputs
Balanced Propagation Delays
Pin and Function Compatible with Other Standard Logic Families
Chip Complexity: FETs = 62, Equivalent Gates = 16
Pb-Free Packages are Available