ADC AD9235BRUZ-40, 1, 12 bit, 105Msps, TSSOP, 28 pines

Single +3 V Supply Operation (2.7 V to 3.6 V)
SNR = 70 dBc to Nyquist at 65 MSPS
SFDR = 85 dBc to Nyquist at 65 MSPS
Low Power: 300 mW at 65 MSPS
On-Chip Reference and SHA
Differential Input with 500 MHz Bandwidth
DNL of ±0.4 LSB
Flexible Analog Input: 1 V p-p to 2 V p-p
Offset Binary or Twos Complement Data Format
Clock Duty Cycle Stabilizer
Pin out Migration to Either AD9215, AD9236, AD9245