Memoria SRAM Infineon, 4Mbit, 512K x 8

CY7C1049GN is a high-performance CMOS fast static RAM device organized as 512K words by 8-bits. Data writes are performed by asserting the Chip Enable (CE) and Write Enable (WE) inputs LOW, while providing the data on I/O0 through I/O7 and address on A0 through A18 pins. Data reads are performed by asserting the Chip Enable (CE) and Output Enable (OE) inputs LOW and providing the required address on the address lines. Read data is accessible on the I/O lines (I/O0 through I/O7). All I/Os (I/O0 through I/O7) are placed in a high-impedance state during the following events: The device is deselected (CE HIGH) The control signal OE is de-asserted.

High speed
tAA = 10 ns
Low active and standby currents
Active current: ICC = 38 mA typical
Standby current: ISB2 = 6 mA typical
Operating voltage range: 1.65 V to 2.2 V, 2.2 V to 3.6 V, and
4.5 V to 5.5 V
1.0 V data retention
TTL-compatible inputs and outputs
Pb-free 36-pin SOJ and 44-pin TSOP II packages